Towards Accelerating Intrusion Detection Operations at the Edge Network usin...

杨利霞

Towards Accelerating Intrusion Detection

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Operations at the Edge Network using FPGAs

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In the current paper, we present our work towards
accelerating intrusion detection operations at the edge network
5 f- q5 k5 E3 K+ q; p  K; zusing FPGAs. Cloud computing and network function
virtualization have led to a new appealing paradigm for service
delivery and management. Unfortunately, this paradigm fails
: ?. [( Z2 K9 Jto correctly support IoT applications and services that seek
  g6 _+ T4 \6 G' m* i! r. `# ?' ybetter communication platforms. Security as a Service can also
be seen as a cloud-based model that needs to be accommodated
  R- A$ a  W4 J) P9 h5 gto fulfill these services requirements. Again, one of the main
- ~4 ~$ Y7 o! G; d& _7 J7 {issues to be addressed in this context is how to improve the
) a. G7 b4 ]' E' h- n" rperformance of such systems or services in order to make them
capable of coping with the huge amount of data while
+ B: h. F# F; ]. H7 c& u: I2 s) {! hremaining reliable. A potential solution is the FPGA based
edge computing, which is a powerful combination offering
FPGA acceleration capabilities together with edge and fog
1 n7 z( s5 q" x/ H5 B$ B7 `benefits. Indeed, our work focusses on devising an Intrusion
* x. r) ~' e) U: _Prevention architecture called FORTISEC (40SEC), that is
# ~2 x  F  U0 Q( A1 O  N6 X/ Imeant to operate in a completely softwarized as well as in an
# b% C: e, T% f! ^FPGA mode. Thereby, we present suitable algorithms, design
- _1 ~$ g3 X6 n* ^5 m$ yprinciples and well defined components towards the
implementation of accelerated intrusion prevention on the
; \% L( ?& [+ qedge. We also present a testbed being utilized for the
implementation of 40SEC and its performance testing.
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