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Towards Accelerating Intrusion Detection
I: G2 A2 q* j( G% U; {Operations at the Edge Network using FPGAs
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In the current paper, we present our work towards
& H" Z. Z* N5 ]8 `% T% `9 Baccelerating intrusion detection operations at the edge network ; M4 d6 e2 {0 d- S
using FPGAs. Cloud computing and network function 1 D( O" y. I) i8 |: \
virtualization have led to a new appealing paradigm for service
$ R4 z% f. e* ]' n1 l2 d) Odelivery and management. Unfortunately, this paradigm fails ( ^" k* D; x2 d. P- Y0 v
to correctly support IoT applications and services that seek 2 K; W8 D ?: L* u# j3 ` V
better communication platforms. Security as a Service can also % G8 A8 X+ O1 R: {, ]
be seen as a cloud-based model that needs to be accommodated , `$ H- p. e$ r
to fulfill these services requirements. Again, one of the main
8 |( y; f* U+ m# hissues to be addressed in this context is how to improve the 9 P5 G- K, I$ w! v- X
performance of such systems or services in order to make them - H9 J) v5 d/ j" O
capable of coping with the huge amount of data while
, H! R8 J1 R( y( o+ Premaining reliable. A potential solution is the FPGA based
) c, ^. \6 m1 L$ {* c/ nedge computing, which is a powerful combination offering
2 G; L o, E/ N& l4 |! G5 e1 t: BFPGA acceleration capabilities together with edge and fog
' x' ?3 W8 x& a6 g( q1 _ wbenefits. Indeed, our work focusses on devising an Intrusion
& R/ y6 t2 I D" U+ `9 |6 H YPrevention architecture called FORTISEC (40SEC), that is ; A: X) M) }/ e
meant to operate in a completely softwarized as well as in an 6 L! [) o+ k* g4 t7 n
FPGA mode. Thereby, we present suitable algorithms, design 8 x0 E+ h" Z: n& L. L9 L
principles and well defined components towards the ' b. h1 }9 n3 f1 p
implementation of accelerated intrusion prevention on the + m6 U7 g( r g3 h7 w
edge. We also present a testbed being utilized for the & `: A2 l+ |) J8 b' v8 R) [
implementation of 40SEC and its performance testing.
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