Towards Accelerating Intrusion Detection Operations at the Edge Network usin...

杨利霞

Towards Accelerating Intrusion Detection

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Operations at the Edge Network using FPGAs

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0 v* c+ A5 m7 I In the current paper, we present our work towards
; W2 R* a$ a* R$ W2 U7 daccelerating intrusion detection operations at the edge network
using FPGAs. Cloud computing and network function
7 g, P* l6 C  V  J! j% m# mvirtualization have led to a new appealing paradigm for service
1 C1 P: B" }  K, I! u) T; edelivery and management. Unfortunately, this paradigm fails
% p0 C" f, R/ G1 N  vto correctly support IoT applications and services that seek
better communication platforms. Security as a Service can also
1 d7 B' V7 u6 K% V$ Ibe seen as a cloud-based model that needs to be accommodated
! [! S: c3 h( j# L' g" rto fulfill these services requirements. Again, one of the main
issues to be addressed in this context is how to improve the
performance of such systems or services in order to make them
4 H; |  ^$ s- e$ ocapable of coping with the huge amount of data while
remaining reliable. A potential solution is the FPGA based
# V# ^7 ]8 [0 x$ x  a& s% tedge computing, which is a powerful combination offering
( z& y! L+ t4 d4 b: z( c( Z% y( t! JFPGA acceleration capabilities together with edge and fog
benefits. Indeed, our work focusses on devising an Intrusion
Prevention architecture called FORTISEC (40SEC), that is
; c2 j, a: {3 Imeant to operate in a completely softwarized as well as in an
FPGA mode. Thereby, we present suitable algorithms, design
principles and well defined components towards the
0 a% E3 E; _$ l% p: w# rimplementation of accelerated intrusion prevention on the
- v. Z5 E" a0 T- a6 H/ xedge. We also present a testbed being utilized for the
implementation of 40SEC and its performance testing.
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