Towards Accelerating Intrusion Detection Operations at the Edge Network usin...

杨利霞

Towards Accelerating Intrusion Detection

Operations at the Edge Network using FPGAs

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In the current paper, we present our work towards
accelerating intrusion detection operations at the edge network
1 ~" y3 J$ j! [4 `) R5 T2 C5 _using FPGAs. Cloud computing and network function
4 y7 r) X# [# w7 d$ k6 p- y7 }virtualization have led to a new appealing paradigm for service
% U4 X* }% \% C7 x1 R4 m8 Q  E* _# Sdelivery and management. Unfortunately, this paradigm fails
to correctly support IoT applications and services that seek
" ]- {" K7 a4 B. e" f5 \. Y8 Vbetter communication platforms. Security as a Service can also
be seen as a cloud-based model that needs to be accommodated
8 x0 u' o* B4 O1 t# Yto fulfill these services requirements. Again, one of the main
issues to be addressed in this context is how to improve the
+ q+ j/ x1 t, B0 p% s8 y5 |" Lperformance of such systems or services in order to make them
capable of coping with the huge amount of data while
remaining reliable. A potential solution is the FPGA based
edge computing, which is a powerful combination offering
FPGA acceleration capabilities together with edge and fog
benefits. Indeed, our work focusses on devising an Intrusion
( C+ r. z" n( v/ |" _' IPrevention architecture called FORTISEC (40SEC), that is
+ x3 V- w8 v  a9 j# O7 G. s5 mmeant to operate in a completely softwarized as well as in an
/ R! Z: y1 L$ HFPGA mode. Thereby, we present suitable algorithms, design
- {8 r& }' A' f9 M5 w! V6 h, hprinciples and well defined components towards the
; ^9 k( Q0 C4 q$ f/ Rimplementation of accelerated intrusion prevention on the
9 t& q8 f4 t) W1 U6 ~% G. O- u( v8 \edge. We also present a testbed being utilized for the
implementation of 40SEC and its performance testing.